Verilog & Testbenches — Intermediate

Curated: move from reading digital logic to writing it — real Verilog RTL with always blocks, blocking vs non-blocking assignment, finite state machines, and testbenches — from a top free video course, then practice in a free in-browser simulator and get certified. The second module of the FPGA/HDL track.

Module version 0.1.0 · 1 lesson

1. Lesson 1

   2 slides
   Study guide — what to focus on

   ~15 min