Verilog & Testbenches — Intermediate
Curated: move from reading digital logic to writing it — real Verilog RTL with always blocks, blocking vs non-blocking assignment, finite state machines, and testbenches — from a top free video course, then practice in a free in-browser simulator and get certified. The second module of the FPGA/HDL track.
Hardware Modelling using Verilog
NPTEL — IIT Kharagpur (Prof. Indranil Sengupta) · video · ~20h · Free · English
Why we picked it: The most widely recommended free intermediate Verilog video course for actually writing RTL. Taught by Prof. Indranil Sengupta at IIT Kharagpur and delivered through NPTEL — India's national MOOC platform run by the IITs/IISc, one of the largest and most-enrolled sources of free engineering courses in the world. This ~42-lecture series is highly rated and heavily used (catalogued and reviewed on Class Central, mirrored on the official NPTEL playlist), and it moves past 'what is a gate' into the real craft: modelling styles, procedural (always) blocks, blocking vs non-blocking assignment, finite state machines, and writing testbenches to simulate a design. It teaches the language and the design discipline together, which is exactly the intermediate step after the first FPGA/digital-logic module.
- the Verilog module — ports, structure, and instantiation
- data types: nets (wire) vs variables (reg) and where each is legal
- continuous (assign) vs procedural (always) modelling styles
- combinational always @(*) and clocked sequential always @(posedge clk)
- blocking (=) vs non-blocking (<=) assignment and why it matters
- modelling finite state machines (FSMs)
- writing Verilog testbenches and applying stimulus
- simulation vs synthesis, plus datapath/control and memory modelling
Study guide
Open the study guide →1 study section · what to focus on + prove it in Forge, then take the check.