FPGA Design & Timing (Advanced)

Curated: go past writing RTL and learn how a design actually becomes fast, working hardware — FPGA architecture (LUTs/FFs/BRAM/DSP), the synthesis-to-place-and-route flow, static timing analysis and closing timing (setup/hold, clock skew, Fmax), pipelining for speed, clock-domain crossing, and a softcore-processor application — from the top-rated free FPGA course, practised in a free HDL simulator and free vendor tools, then certified. The advanced module of the FPGA/HDL track.

Module version 0.1.0 · 1 lesson

1. Lesson 1

   2 slides
   Study guide — what to focus on

   ~15 min