FPGA Design & Timing (Advanced)
Curated: go past writing RTL and learn how a design actually becomes fast, working hardware — FPGA architecture (LUTs/FFs/BRAM/DSP), the synthesis-to-place-and-route flow, static timing analysis and closing timing (setup/hold, clock skew, Fmax), pipelining for speed, clock-domain crossing, and a softcore-processor application — from the top-rated free FPGA course, practised in a free HDL simulator and free vendor tools, then certified. The advanced module of the FPGA/HDL track.
Introduction to FPGA Design for Embedded Systems
University of Colorado Boulder (Coursera) · video · ~19h · Free · English
Why we picked it: The highest-rated, most-reviewed FPGA course online (4.6 stars from ~1,200 ratings, University of Colorado Boulder) and free to audit — 'Enroll for Free' gives you the full video lectures. Despite the beginner-sounding name it is really a tour of the FPGA *implementation flow*: it starts from the silicon (LUTs, logic cells, on-chip memory) and walks the whole Quartus tool chain — synthesize, compile, place-and-route, simulate in ModelSim, and close timing in the TimeQuest static timing analyzer — then teaches the two techniques this module cares about most: improving timing with pipelining, and dropping in IP to build a real application (a NIOS II softcore processor via Qsys). That makes it the natural 'advanced' step after HDL and testbenches: it takes RTL you can already write and shows how it becomes fast, closed-timing hardware on a real device.
- FPGA architecture from the ground up: LUTs, logic cells, flip-flops, and on-chip memory (SRAM- vs FLASH- vs anti-fuse-based devices)
- the FPGA design flow — synthesis, compilation, and place-and-route onto physical device resources
- viewing the synthesized RTL and simulating a design in ModelSim
- static timing analysis and timing closure with the TimeQuest timing analyzer
- reading timing results: setup/hold, clock relationships, and maximum clock frequency (Fmax)
- improving timing with pipelining
- improving productivity by integrating IP blocks
- building an application: a NIOS II softcore processor system with the Qsys system-integration tool
Study guide
Open the study guide →1 study section · what to focus on + prove it in Forge, then take the check.