Study guide — what to focus on

This module is curated — the teaching is a top free course (linked in the card above); our job is to point you at the right things, make you prove it, and certify you. This one is intermediate: you already know how to make KiCad route a board. Now the goal is a board that works under load and can actually be manufactured.

The plan

1. Watch the course (the card above). Don't memorise clicks — watch why each layout decision gets made on a real multi-layer board.
2. Focus on these — they're what the check tests and what separates a working board from a pretty one:
   • Stackup — why signal layers sit next to solid ground/power planes on a 4-layer board.
   • Ground planes & return paths — fast return current flows directly under the trace, so never route a high-speed signal across a gap or split in its reference plane.
   • Track width vs. current — power and ground nets get wide copper (lower resistance, less heat); signals can be thin.
   • Decoupling placement — bypass caps go right at the IC power pin, short path to ground; distance kills their benefit.
   • Controlled impedance (intro) — impedance is set by geometry (trace width, dielectric height to the plane), which is why fast nets need a defined stackup.
   • Vias — each one adds inductance and a discontinuity; minimise layer changes on fast nets and stitch grounds near via transitions.
   • DFM — design to your fab's real limits: minimum trace/space, annular ring, and copper-to-edge clearance.
   • Thermal — copper pour + thermal vias pull heat out of hot power parts.
3. Prove it in Forge (next section) — design a mixed power-and-signal board and read it with a layout eye.
4. Take the K-Check to earn your certificate.

Why this connects to building real products

This is the difference between a board that passes DRC and a board you'd actually put in a product. When you hit Build in Forge and a design goes to fab, these are the rules the board house checks against — trace/space, annular ring, copper-to-edge, thermals. A layout that ignores return paths or crams copper to the edge either radiates noise, runs hot, or comes back from the fab as a scrapped panel. Learning to see the ground plane, the decoupling, and the manufacturable clearances is what lets you trust the boards you send to fabrication — and, later, push back on a layout that won't hold up.

Time to apply the layout eye. The course showed you good layout on a real multi-layer board; now design one of your own and read it like a layout engineer.

Send the prompt below in Forge Design — a USB-C ESP32 board with a regulator, an I2C IMU, and an addressable-LED output — and watch it pull together mixed power and signal on one board.

As you read the result, map it to the course: which nets deserve wide tracks (power, ground, the LED string), where the ground plane belongs, and where the decoupling caps sit relative to each IC power pin. That instinct — seeing the layout before you route it — is the whole point.