Study guide — what to focus on

This module is curated — the teaching is a top free talk (linked in the card above); our job is to point you at the right things, make you prove it, and certify you. This is the advanced high-speed step, so it assumes you've already done basic layout and DFM (pcb-layout-dfm).

The plan

1. Watch the talk (the card above). It's long but worth every minute — you don't need to memorise it, aim to rewire your intuition around the ideas below.
2. Focus on these — they're what the check tests and what separates a board that works from one that radiates and rings:
   • There is no ground — only return current. Every signal that flows out must flow back; your whole job is to control where it returns.
   • Return current hugs the trace. At high frequency it flows directly under the trace on the adjacent reference plane (least inductance), keeping the loop tiny.
   • Controlled impedance — trace width, dielectric height to the reference plane, copper thickness and Er set a microstrip/stripline's impedance. Length does not.
   • When a trace is a transmission line — it's the edge rate (rise time), not the clock frequency, that decides. Fast edges mean reflections, and reflections mean termination.
   • Crosstalk is field coupling between traces — fix it with spacing and a close reference plane.
   • Never cross a plane gap with a fast signal — the return current detours, the loop explodes, and you get EMI.
   • Stackup & PDN — signal layers adjacent to solid planes; decoupling caps keep the PDN impedance low and the rail quiet.
3. Prove it in Forge (next section) — describe a fast board and read how it's put together.
4. Take the K-Check to earn your certificate.

Why this connects to building real products

This is the layer where a design either survives EMC testing or fails it — and where a fast bus either works first try or glitches intermittently. The unifying idea from the talk is loop area: keep every signal's return current directly beneath it and most signal-integrity and EMC problems disappear at once. In Forge, when you describe a board with a fast MCU, USB, and an external bus, the same physics is in play — knowing return paths and reference planes lets you read why a layout is arranged the way it is, and later drive those decisions yourself.

Time to apply it. The talk changed how you see a board; now design one where those choices actually bite — a fast microcontroller, USB, and an external bus to memory or a display.

Send the prompt below in Forge Design, then read the result like a signal-integrity engineer: where does each fast signal's return current flow, which reference plane is it hugging, and which nets are the ones you'd want on controlled impedance with decoupling close by?

That mapping — the physics from the talk onto a real design — is the whole point of this module.