Study guide — what to focus on

This module is curated — the teaching is a top free video series (linked in the card above); our job is to point you at the right things, make you practice them, and certify you.

The plan

1. Watch the series (the card above). You don't need to memorise it — aim to understand the ideas below.
2. Focus on these — they're what the check tests and what you'll actually use:
   • Logic gates & truth tables — AND, OR, NOT, NAND, NOR, XOR, and reading off what each outputs.
   • Boolean algebra — the basic identities (e.g. A + A' = 1, A · 1 = A) you use to simplify logic.
   • Combinational vs. sequential — combinational logic depends only on now; sequential logic has memory (state) and is driven by a clock.
   • Flip-flops & clocks — the D flip-flop as a 1-bit store that captures its input on the clock edge; how registers and state machines are built from them.
   • Verilog basics — the module (ports in/out), assign for combinational logic, and always @(posedge clk) for clocked/sequential logic.
   • Binary — reading binary numbers, since every signal is 1s and 0s.
3. Practice in an online simulator (next section) — write a little Verilog and simulate it in the browser, no install needed.
4. Take the K-Check to earn your certificate.

Why this matters

Digital logic is the layer underneath every microcontroller, sensor, and chip you'll ever design with. Verilog is how engineers describe that logic as text and turn it into real hardware on an FPGA — programmable silicon you can reconfigure at will. Getting fluent with gates, flip-flops, and a first module gives you the vocabulary to reason about how digital parts behave, to read a datasheet's timing and logic, and — down the track — to design your own custom digital blocks instead of only wiring up someone else's.

The best way to make Verilog stick is to write and simulate it — and you can do that free in your browser, with nothing to install. Open EDA Playground, a free online HDL editor and simulator: pick a Verilog/SystemVerilog testbench template on the left, type your design and a small testbench, hit Run, and read the simulation output (and optional waveforms).

For a first exercise, build something tiny and combinational — say a 2-input gate or a 2-to-1 multiplexer — in a module, drive its inputs from a testbench, and confirm the outputs match the truth table. Once that works, try a sequential design: a small counter or a single D flip-flop clocked with always @(posedge clk), and watch its value step on each clock edge. That loop — write a module, simulate it, check the result against what you expected — is exactly how real digital design works, just scaled down.